The present disclosure relates to integrated circuit devices, and more specifically, to measuring current and resistance of integrated circuit devices using combined diode/resistor structures to monitor integrated circuit manufacturing process variations.
Small changes in the manufacturing process of integrated circuits can have large consequences, which may detrimentally affect the performance of the individual integrated circuit devices. Therefore, it is often useful to include devices that can be tested during or after the manufacturing process. For example, some measurements that are useful when testing integrated circuit devices include resistance and current flow. The testing devices can highlight different performance characteristics that result from changes in the manufacturing process. The devices and methods described below help monitor the changes that occur within integrated circuit devices when the manufacturing process is altered.
The present disclosure relates to capacitors, and, more particularly, to a metal-insulator-metal capacitor with deep trench structure and method of forming the structure with silicon-on-insulator technology.
Trench capacitors are widely used in various semiconductor applications. For example, embedded dynamic random access memory (DRAM) technology, in which trench capacitors can be used, has played an important role in the emerging system-on-chip (SoC) products. Significant system performance gains have been demonstrated by integrating the embedded DRAM and logic units on the same chip. Given the enormous success of embedded DRAM technology achieved on bulk silicon substrates, integrating embedded DRAM with silicon-on-insulator (SOI) technology will further boost the performance of high-end SOI server chips. Substrate resistance, however, can limit both DRAM and deep trench capacitance behavior.
A typical deep trench capacitor comprises a deep trench in a semiconductor substrate (e.g., the semiconductor substrate of either a bulk silicon wafer or silicon-on-insulator (SOI) wafer). Typically, a doped region within the substrate adjacent to the trench forms one capacitor plate (i.e., a buried capacitor plate). A dielectric layer lining the trench forms the capacitor dielectric. Finally, a conductive fill material (e.g., a doped polysilicon) within the trench forms another capacitor plate. A standard contact can be formed to the capacitor plate within the trench. However, a number of additional processing steps are required to form the buried capacitor plate contact.
For example, if a bulk silicon wafer is used, then the deep trench capacitor must be formed such that it extends through an N-doped diffusion connector (e.g., an NWELL) in the silicon substrate. Next, a feature is patterned in the NWELL at the top surface of the silicon substrate and a contact is formed to this patterned silicon feature. Similarly, if a silicon-on-insulator (SOI) wafer is used, then the deep trench capacitor must be formed such that it extends through an N-doped diffusion connector (e.g., an NBAND) below the buried oxide (BOX) layer. Next, a patterned doped polysilicon feature is formed that extends through the BOX layer to the NBAND and a contact is formed to this polysilicon feature.
In either case, due to the requirement of an N-doped diffusion connector, circuit design flexibility is sacrificed. Furthermore, in either case photolithographic techniques must be used to pattern a feature to the N-doped diffusion connector. Consequently, the ground rules for these additional processing steps must take into account overlay tolerances between the contact structures and the deep trench capacitor itself, critical dimension tolerances, the minimum allowable distance between the buried trench and the boundary of the n-doped diffusion connector, etc. Consequently, process windows are small and the sizes of the various circuits that incorporate such deep trench capacitors (e.g., SRAM cells) are not optimized.